[libre-riscv-dev] kestrel kcp53000 developer making a nmigen RISC-V core

[Jacob Lifshay]

On Tue, Apr 9, 2019, 21:15 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Wed, Apr 10, 2019 at 4:20 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> >
> > I spent a little time to look through this, I'll look more later.
>
>  cool.  i'm in touch with samuel, the developer: he's going to write a
> nmigen front-end for the PLU (FSM) engine that he created, allowing
> him to *auto-generate* the majority of the CPU from this existing
> (proven) file:
>
> https://github.com/KestrelComputer/polaris/blob/master/processor/rtl/SMG/seq.smg
>
neat

>  the PLU-style FSM he based on studies of how the 6502 works.  i could
> have the acronym wrong....
>
I think you meant PLA.

>
> it's an amazing approach, that only a software engineer would come up
> with when faced with the challenge of designing a processor :)
>


just thought it would be really neat to write a program that's a processor
compiler (like LLVM, but for digital logic) in that you feed in the
definition of the ISA and the ALUs and it automatically generates a
processor including all the pipelines, forwarding, stalling, and other
logic. I was halfway hoping that samuel's code would be that impressive.