[libre-riscv-dev] Fwd: spike simple-v implementation, refinement needed

[Jacob Lifshay]

forgot to add mailing list

---------- Forwarded message ---------
From: Jacob Lifshay <programmerjake at gmail.com>
Date: Fri, Sep 28, 2018, 13:13
Subject: Re: [libre-riscv-dev] spike simple-v implementation, refinement
needed
To: Luke Kenneth Casson Leighton <lkcl at lkcl.net>


Setting csrs doesn't necessarily create a pipeline stall, at least it
doesn't in my rv32 core (probably not a good example).

https://github.com/programmerjake/rv32

On Thu, Sep 27, 2018, 20:14 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Fri, Sep 28, 2018 at 3:36 AM, Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
>
> > one possibility: have a separate CSR that sets a register which is to
> > be allocated *AS* vl.
> >
> > i'll have to think about this and raise some further discussion.
>
>  a message from bruce mentioned that setting CSRs creates a pipeline
> stall, so it's going to be necessary to have an actual instruction,
> SETVL. it's going to need to be an I-type, i'll investigate how to add
> instructions to spike.
>
> l.
>
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