[libre-riscv-dev] Fwd: spike simple-v implementation, refinement needed

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68


On Fri, Sep 28, 2018 at 9:14 PM, Jacob Lifshay <programmerjake at gmail.com> wrote:

> Setting csrs doesn't necessarily create a pipeline stall, at least it
> doesn't in my rv32 core (probably not a good example).
>
> https://github.com/programmerjake/rv32

 yep krste corrected bruce on isa-dev.  what i may do is have two
CSRs, one to set MVL, the other to set VL.  one of the issues with SV
is that MVL (max vector length) is flexible where in RVV it's a
hardware set/fixed limit.

l.