[libre-riscv-dev] spike simple-v implementation, refinement needed

[Luke Kenneth Casson Leighton]

On Fri, Sep 28, 2018 at 3:36 AM, Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> one possibility: have a separate CSR that sets a register which is to
> be allocated *AS* vl.
>
> i'll have to think about this and raise some further discussion.

 a message from bruce mentioned that setting CSRs creates a pipeline
stall, so it's going to be necessary to have an actual instruction,
SETVL. it's going to need to be an I-type, i'll investigate how to add
instructions to spike.

l.