[libre-riscv-dev] spike-sv non-default element widths

[Jacob Lifshay]

Note that the W and D opcodes sign extend not because they are special
sign-extending opcodes and the rest are zero-extending, it because the W
and D opcodes produce results less than XLEN bits, and the canonical way to
store smaller values in integer registers in RISC-V is sign-extension.
Notice that the results are still sign-extended even for ops like UDIVW
which is Unsigned division.

For coming up with the extension/truncation order for instructions, I'd use:

RS1 @ rs1 bits, sign-extended to max(rs1, rs2, rd) bits
RS2 @ rs2 bits, sign-extended to max(rs1, rs2, rd) bits
add/sub/mul/div/etc. @ max(rs1, rs2, rd) bits
RD @ rd bits, truncate to rd bits.

If the same results are produced, a smaller number of bits can be used for
the intermediate values, but it must behave as-if the preceding algorithm
was followed.

Alternatively, I would sign-extend/truncate to rd bits and do the operation
at rd bits.

Jacob


On Tue, Oct 23, 2018 at 8:44 PM lkcl <lkcl at libre-riscv.org> wrote:

> ... nope, i really can't think of anything that would stop the overlap
> between RV32 and RV32I instructions once element-widths start getting
> over-ridden, apart from the critically important thing of respecting
> that an opcode that ends in "W" must do sign-extension instead of
> zero-extension.
>
> jacob could you advise if you think that the order should be:
>
> * RS1 @ rs1 bits, sign-extended to max(rs1, rs2) bits
> * RS2 @ rs2 bits, sign-extended to max(rs1, rs2) bits
> * add @ max(rs1, rs2) bits
> * RD @ rd bits. sign-extend to rd if rd > max(rs1, rs2) otherwise truncate
>
> or anything different from that (in similar step-by-step fashion)?
>
> l.
>
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