[libre-riscv-dev] spike-sv non-default element widths

[lkcl]

... nope, i really can't think of anything that would stop the overlap
between RV32 and RV32I instructions once element-widths start getting
over-ridden, apart from the critically important thing of respecting
that an opcode that ends in "W" must do sign-extension instead of
zero-extension.

jacob could you advise if you think that the order should be:

* RS1 @ rs1 bits, sign-extended to max(rs1, rs2) bits
* RS2 @ rs2 bits, sign-extended to max(rs1, rs2) bits
* add @ max(rs1, rs2) bits
* RD @ rd bits. sign-extend to rd if rd > max(rs1, rs2) otherwise truncate

or anything different from that (in similar step-by-step fashion)?

l.