[libre-riscv-dev] spike-sv non-default element widths

[lkcl]

On Sun, Oct 21, 2018 at 8:53 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> On Sun, Oct 21, 2018, 09:42 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:

> It just depends on if it's more important to cast after the add or before
> the add. I recommend having it be sign/zero-extended before the add as an
> explicit cast instruction can be used if after-the-add is needed, whereas
> two are necessary if we use visa-versa.

 ok, so the case that i may have missed in the "s/z-ext after" is
where 0x3f (12-bit signed-immed) is added to 0x7f (8-bit rs1), the
result wraps round (as rs1 is only 8-bit) but it is then stored in a
64-bit result.  the *expected* behaviour would be, i feel, that 0x3f
should be sign-extended to 64-bit, and rs1 likewise.

if however rd is *also* only 8-bit, *then* truncating is fine.

y'know... there's one other option, which i was resisting quite a lot,
however after reading chapter 6 on multiply, about how MULH[S][U] may
be macro-op fused with MUL, where those two instructions may be used
on e.g. RV64 to create a full 128-bit answer.

the idea behind the whole RV64I concept seems to be to be able to
construct unsigned-unsigned, unsigned-signed and signed-signed
arithmetic by splitting a 32-bit operand into two halves.  that could
hypothetically be a characteristic that's preserved, even through the
polymorphic width changes?

l.