[libre-riscv-dev] spike-sv non-default element widths

[lkcl]

On Wed, Oct 24, 2018 at 9:27 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> Note that the W and D opcodes sign extend not because they are special
> sign-extending opcodes and the rest are zero-extending, it because the W
> and D opcodes produce results less than XLEN bits, and the canonical way to
> store smaller values in integer registers in RISC-V is sign-extension.

 interesting.  makes sense

> Notice that the results are still sign-extended even for ops like UDIVW
> which is Unsigned division.

 duvuw, you mean.  and yes, i see that - section 6.2 of the spec, as
it's a 32-bit quotient.

> For coming up with the extension/truncation order for instructions, I'd use:
>
> RS1 @ rs1 bits, sign-extended to max(rs1, rs2, rd) bits
> RS2 @ rs2 bits, sign-extended to max(rs1, rs2, rd) bits
> add/sub/mul/div/etc. @ max(rs1, rs2, rd) bits
> RD @ rd bits, truncate to rd bits.
>
> If the same results are produced, a smaller number of bits can be used for
> the intermediate values, but it must behave as-if the preceding algorithm
> was followed.
>
> Alternatively, I would sign-extend/truncate to rd bits and do the operation
> at rd bits.

 i thought about this algorithm, and i wondered how it would be
possible to ensure compatibility with the existing default "truncate
to 32-bit" behaviour of RV32I (or "truncate to 64-bit" for RV64I which
is *planned* for RV128).

if the max is taken of rs1 *and* rs2 *and* rd, the default behaviour
of RV32I cannot be attained, as the op would take place at
rd-bitwidth, and be stored *as* rd-bitwidth.

so i think, really, it's going to have to be max(rs1, rs2) for the
add, then sign-ext from that up to rd [or truncate down].


what's particularly annoying is that for the standard RV32 group of
arithmetic instructions (chapter 2), arithmetic operations are almost
all done @ XLEN bits, however for RV32I they're all done at 32-bit
(and then sign-extended).

so when specifying the default width algorithm, it's:

* if opcode is in the RV32 group, rd, rs1 and rs2 bitwidth are XLEN if
elwidth==default
* if opcode is in the RV32I group, rd, rs1 and rs2 bitwidth are *32*
if elwidth == default

annoying that the bitwidth default will change depending on the type of opcode.

l.