[libre-riscv-dev] MAXVECTORLENGTH could be longer

[Luke Kenneth Casson Leighton]

On Tue, Oct 16, 2018 at 10:24 AM Jacob Lifshay <programmerjake at gmail.com> wrote:

> The current SimpleV spec defines MAXVECTORLENGTH as XLEN - 1 producing 31
> and 63 on RV32 and RV64 respectively. I think it would be better to have it
> be just XLEN as there is enough space in the registers used for predication
> and you can easily get more than 64 elements by operating on packed 8-bit
> elements or by using the extended (past r31) registers.

 ok that's sorted, so both MVL and VL span from 1..XLEN rather than 0..XLEN-1

 it means that CSRRW to SVSTATE, VL and MVL are now rather... odd (or
VL and MVL are), as the value returned from CSRRWI SV, 3 will put the
value *4* into VL... going to have to think about that a bit more.

l.