[libre-riscv-dev] MAXVECTORLENGTH could be longer

[Luke Kenneth Casson Leighton]

On Tue, Oct 16, 2018 at 11:46 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

>  it means that CSRRW to SVSTATE, VL and MVL are now rather... odd (or
> VL and MVL are), as the value returned from CSRRWI SV, 3 will put the
> value *4* into VL... going to have to think about that a bit more.

 ok i think i got it, CSRRWI on VL and MVL, and CSRRW on STATE have to
add 1 to MVL and SVL on set, STATE has to *subtract* 1 from MVL and VL
on returning the (old) value; CSRRW on MVL and VL on the other hand do
*not* subtract or add 1, however if CSRRW tries to set VL or MVL to
zero an exception has to be thrown.

l.