[libre-riscv-dev] MAXVECTORLENGTH could be longer

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Tue, Oct 16, 2018 at 10:24 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> The current SimpleV spec defines MAXVECTORLENGTH as XLEN - 1 producing 31
> and 63 on RV32 and RV64 respectively. I think it would be better to have it
> be just XLEN as there is enough space in the registers used for predication
> and you can easily get more than 64 elements by operating on packed 8-bit
> elements or by using the extended (past r31) registers.

 yes i'm just in the process of adding STATE / CFG CSRs which switch
off SV entirely, and that would in turn allow VL and MVL to be set to
0 to indicate "VL of 1", 1 to indicate "VL of 2" and 63 to indicate
"VL of XLEN".

 the problem is that the number of bits is so tight (STATE CSR) that
allowing each of the offset, VL and MVL to be 7 bit just to be able to
store the value "64" 0b1000000, that there would not be enough space
to do so.

 so, instead, am keeping them to 6 bits, and consequently they can be
offset by 1.  it'll be... odd, but it means 1 less CSR needed when it
comes to setup and context-switching.

l.