[libre-riscv-dev] SV C.LWSP / C.SWSP becomes "vector unit stride"

[Luke Kenneth Casson Leighton]

ok so with a little bit of thought (and a unit test to confirm),
c.lwsp has effectively become a "vector unit stride" operation.  as it
is twin-predicated, it can be used as a compact, sparse version of
LOAD-MULTI / STORE-MULTI.

what this involved is: if SP (x2) is marked as vectorised, the actual
*OFFSET* advances, *NOT* the register number, during the internal
parallelisation loop.  so this:

 c.lwsp t0, 12(sp) # assume both t0 and sp are marked as vectors

actually would result in the following (equivalent) operations:

 c.lwsp t0, 12(sp)
 c.lwsp t1, 16(sp)
 ....
 ....


also - and care is going to have to be taken here - redirection is
still possible, so instead of x2 (sp) *being* sp, it could target any
desired register.  however any operations actually involving the stack
would also be redirected, so a *lot* of care has to be taken.

i'm honestly not sure if this is a good idea or not.  LW - the
operation that C.LWSP is supposed to mirror - is belng left alone,
i.e. LW is *not* similarly converted to a vectorised unit stride.

l.