[libre-riscv-dev] sv branch predication

[Luke Kenneth Casson Leighton]

so i've been thinking how make branch predication useful and flexible.
it's already a little odd, as it's an overload of BEQ, BNE and so on,
giving it slightly different meaning.  BEQ r1, r2, #jumppoint has two
registers, so there's the opportunity to have two predicate entries:
one on the first register, which is the main one, and i decided to
make the one on the _second_ register specify the *target* predicate
which stores, as a bitfield, the results of the element compares.

that leaves two bits "spare" from the Pred CSR: the invert and the
zeroing bits, which are redundant (useless) at the moment.

what i figured was:

* use the "inversion" bit to indicate that the relevant comparison
result predicate bit is *cleared* in the target if the compare is
successful and the invert bit is true, otherwise the result predicate
bit is *set* if the compare is successful.
* use the "zeroing" bit to indicate that (as mentioned previously with
the strcmp example pseudocode), if any compare fails, the
vectorisation loop ends early.

i believe that gives the possibility of covering AND, OR, NAND and NOR
behaviour, with an extra jump, or using BEQ instead of BNE.  also i
think overloading the "zeroing" bit gives the ability to jump out of
ANDed if comparisons, just like would normally be optimised by a
compiler: if there is a chain of boolean tests being ANDed together
and one of them fails, you don't need to even bother to calculate any
of the subsequent ones.

so... that's where i'm at.

l.