[libre-riscv-dev] Regarding the patch

[Luke Kenneth Casson Leighton]

On Sun, Nov 18, 2018 at 6:10 AM Daniel Benusovich
<flyingmonkeys1996 at gmail.com> wrote:
>
> The change to the macro SV_ELWIDTH_TEST is complete and pushed.
> An issue I see is in files such as sv_ld_elwidth.S the instruction are formatted like so:
>>
>> inst   x28, 0(x12);
>
>
> which can pose an issue when trying to standardize the testing macro. Perhaps adding a second parameter that selects the format of the instruction to be tested? The parameter field is getting a bit out of hand already it is at 14!

 yeah, the next phase is, write a macro that calls that macro.
SV_LDD_ELWIDTH_TEST and SV_LDW_ELWIDTH_TEST

> Is adding anymore a good idea even? I imagine a seperate macro would be written for each format of the instructions:
>>
>> code   x28, x15, x12;
>>
>>  inst   x28, 0(x12);
>
> And then have the writer pass the macro selection. I wanted to bounce it off you first before I went into that.

 see some of the entries in test_macros.h they actually pass in much
more complex "code".  as in, *actual* code.  see TEST_CASE macro.

 so yes, further macros, calling macros, calling macros.

 remember though, go *one* step at a time!  one very very simple
commit.  then another, then another, then another, with a full rebuild
"make clean; make run" in between.


>> convert the files here one-by-one to litex
>>  https://github.com/programmerjake/rv32
>
>
> I saw in the mainling list a reference to migen/litex do you mean this guy here that is python based?
> https://github.com/m-labs/migen

 yes.

> or this guy who is also python based?
> https://github.com/timvideos/litex-buildenv

 litex is better, it can do things like this:
https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/vexriscv/core.py

 which is importing the vexriscv verilog core, see lines 105-113 for
an example of linking verilog module args to migen args.  line 128 as
well, for the wishbone connection.

>
> Forgive me as this as the first time I have heard of it was quite recently. Looks very convenient and promising though!

 it's the OO and standard documentation and programming practices of a
modern language... oh and it generates verilog.

 https://www.bunniestudios.com/blog/?p=5018


> And as far as converting is concerned keep the same names/structure and take the logic into the selected language(migen or litex) correct? Is there anywhere in particular the results should go as of yet?

 not yet - just exploring

> Hope you guys are having a good day,

 preeeetty good :)