[libre-riscv-dev] compressed instruction decoder (verilog)

[Luke Kenneth Casson Leighton]

https://github.com/ataradov/riscv/blob/master/rtl/riscv_core.v#L210

located a compressed-16 to non-compressed-32 decoder, it could be a
*lot* tidier, include some constants, however it's a good starting
point, hopefully to save some time.

l.