[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #14 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #13)
> (In reply to Jacob Lifshay from comment #9)
> > I consider CRs weird enough (since they're rarely stored in memory) that
> > they shouldn't be used to decide our in-register layout of vector types,
> 
> very much agreed.
> 
> > instead, we should strive for consistency between registers and memory,
> > since that makes a bitcast, which is commonly assumed to be zero-cost,
> > actually be zero cost.

in SIMD code, bitcasts are actually very common, easily several percent of
operations. I can't say how much that will translate to SV, but it is
significant for performance.

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