[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #9)
> I consider CRs weird enough (since they're rarely stored in memory) that
> they shouldn't be used to decide our in-register layout of vector types,

very much agreed.

> instead, we should strive for consistency between registers and memory,
> since that makes a bitcast, which is commonly assumed to be zero-cost,
> actually be zero cost.

no.  the code works right now.  it gets things right, and it's compliant with
OpenPOWER.

making change for changes sake has a cost (that we cannot afford).

you need to provide a clear use-case such as "10% performance increase will
result with this change which is used in NN% of code and consequently it has
high value"

a bitmanip bytereverse opcode or simply using the appropriate bytereverse ld
should be more than enough.  as should swizzle, in some cases.

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