[Libre-soc-bugs] [Bug 982] Support PowerPC ABI in ISACaller
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Sun Oct 22 22:17:12 BST 2023
https://bugs.libre-soc.org/show_bug.cgi?id=982
--- Comment #130 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #129)
> OK, enabling this bit fixes the SRR1:
>
> SRR1[PIb.TRAP] = 1
hmmm that should *not* be necessary. it is handled by self.TRAP(0xc00)
which is in the system.mdwn pseudocode for sc.
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=75887d596e2d067931382d20b2885d93be86c878
>
> Still no glue about MSR, it has several bits inactive after the code gets
> executed.
yes. that is correct behaviour.
i will have a look at this tomorrow ok?
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