[Libre-soc-bugs] [Bug 982] Support PowerPC ABI in ISACaller

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=982

--- Comment #123 from Dmitry Selyutin <ghostmansd at gmail.com> ---
Folks, these MSR and SRR1 drive me nuts. Could you check, please, what goes
wrong?


There are two commits:

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=b3a3b220fc8815c8d679c7aec48e90002bcd587c

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=6faf325b3f4368a5a93e6944590461c94f404251

Reproducer is:
SILENCELOG=true python3 ./src/openpower/decoder/isa/test_syscall.py | grep
SYSCALL


You can see here the values I expected vs actual ones.

SYSCALL SRR1 0x9000000000002903 0x9000000000022903
SYSCALL  MSR 0x9000000000002903 0x9000000000000001

SRR1 gets its bit 17 set, but I'm struggling to find this bit anywhere. This is
not present in DEFAULT_MSR, and, as it seems, is not even present as MSR field.

MSR gets several bits disabled. Bits 1, 8, 11 and 17 are not present as fields
in MSRb. 


I tried following "4.3.1 System Linkage Instructions" and "7.5.14 System Call
Interrupt" but apparently did something wrong. Any clue?

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