[Libre-soc-bugs] [Bug 865] implement vector bitmanip opcodes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=865

--- Comment #22 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #21)
> (In reply to Jacob Lifshay from comment #20)
> here is the a / neg-a selection anyway:
> 
> +    a1 = RA if mode&1 else ~RA

that's bitwise-not, not neg -- I get you point anyway...
> 
> if i understand correctly, what you are saying is
> that the mode-bits can be "morphed" to do the same
> thing?

sorta...I'm saying you only need 1 mode2 bit.

The idea is that, currently add/subf/etc. are basically:

a = ~RA if subtracting else RA
carry_in = 0
if subtracting:
    carry_in = 1
RT = a + RB + carry_in

bmask would (ignoring mask and bit-reverse and shifting) do:

a = ~RA if imm & 0b1 else RA
b = 1 if imm & 0b10 else -1 # mode2
carry_in = 0
y = a + b + carry_in
v00 = 0
v01 = v10 = bool(imm & 0b100)
v11 = bool(imm & 0b1000)
if v00 == v01 == v10 == v11 == 0:
    raise IllegalInstruction("other instructions can use the spare space")

# 64x 4-in muxes -- basically a binlog operation:
# probably saves gates over muxing over and, or, and xor
table = [v00, v01, v10, v11]
RT = 0
for i in range(64):
    ra_bit = bool(RA & (1 << i))
    y_bit = bool(y & (1 << i))
    RT |= table[(ra_bit << 1) | y_bit] << i

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