[Libre-soc-bugs] [Bug 865] implement vector bitmanip opcodes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=865

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ha!  found them!

https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=7b6eb743caafb5bc6846d2d47c3040025a961460

--- a/openpower/sv/bmask.py
+++ b/openpower/sv/bmask.py
@@ -1,6 +1,7 @@
 def bmask(mode, RA, RB=None, zero=False):
     RT = RA if RB is not None and not zero else 0
     mask = RB if RB is not None else 0xffffffffffffffff
+    RA = RA & mask
     a1 = RA if mode&1 else ~RA
     mode2 = (mode >> 1) & 0b11
     if mode2 == 0:
@@ -22,7 +23,9 @@ def bmask(mode, RA, RB=None, zero=False):
          RT = a1 ^ a2
     return RT & mask

-SBF = 0b001110
+SBF = 0b01010
+SOF = 0b01001
+SIF = 0b10000 # 10011 also works no idea why yet

i'm so happy and full of great joy. w00t. etc.
that's masking working properly *and* covering the
entirety of the x86 BMI1 and TBM bitmanip set,
*in a way that can be used for Vector Masks*.
frickin cool.

now, there's one set of mode-bits (0b11000 -> 0b11111)
which in *theory* could be used for another mode,
like you suggest in comment #3 (shift-down-by-one)

although, to be honest, if it's *really* just "shift-down by one"
or "invert" input or invert output i'm inclined to suggest just
using an extra 32-bit instruction for that.  sradi.

it depends on whether mask interacts with things and makes
life more complex than just "do a shift afterwards"

-- 
You are receiving this mail because:
You are on the CC list for the bug.