[Libre-soc-bugs] [Bug 865] implement vector bitmanip opcodes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=865

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #3)
> we'll also want shifting by 1 bit to cover finding up to and
> including/excluding lowest set bit.

that's 6 mode bits


> x ^ (x - 1) => set up to lowest set bit inclusive
> (x ^ (x - 1)) >> 1 => set up to lowest set bit exclusive
> 
> we'll also want the option to bit-reverse both input and output so we can do
> first set msb rather than first set lsb.

that's 8 mode bits.

this needs 5 bits:

+def bmask(mode, RA, RB=None, zero=False):
+    RT = RA if RB is not None and not zero else 0
+    mask = RB if RB is not None else 0xffffffffffffffff
+    a1 = RA if mode&1 else ~RA
+    mode2 = (mode >> 1) & 0b11
+    if mode2 == 0:
+        a2 = -RA
+    if mode2 == 1:
+        a2 = RA-1
+    if mode2 == 2:
+        a2 = RA+1
+    if mode2 == 3:
+        a2 = ~(RA+1)
+    a1 = a1 & mask
+    a2 = a2 & mask
+    mode3 = (mode >> 3) & 0b11
+    if mode3 == 0:
+         RT = a1 | a2
+    if mode3 == 1:
+         RT = a1 & a2
+    if mode3 == 2:
+         RT = a1 ^ a2
+    return RT & mask

* 10-bits XO is the "norm" for X-Form
* 5-bits XO is the "norm" for high-cost (VA-Form for example), leaving
* 5-bits for Mode

however with a budget of only 10-bits for XO:

* 6-bits mode leaves only 4 bits for XO
* 8-bits mode leaves only 2 bits for XO

the table on the bitmanip page has room - barely - for more opcodes
unless grevlogw is removed

    https://libre-soc.org/openpower/sv/bitmanip/

and even then, it would be without an Rc=1 option.

also i was planning to add a "merge" option L=1 (zero=True/False
in the pseudocode above) if practical which leaves only 1 bit
and that's an entire Major Opcode for the entire
instruction.

the only other alternative is to start absorbing some of the 5-XO-bit
portions of Major 19, Major 31 etc. which if we propose too many of
those the ISA WG is going to get pissed.

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