[Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=671

--- Comment #66 from dmitry.selyutin at 3mdeb.com ---
(In reply to Jacob Lifshay from comment #65)
> If we did just decide to skip some instructions just because we'd have to
> modify the spec text, I think the people on the ISA WG reviewing how SV
> works would take that as evidence of SV being inconsistently applied and
> half-baked, increasing our chances of rejection.

Jacob, it looks like if you've skipped parts of my messages. Here are relevant
parts, please, check.

https://bugs.libre-soc.org/show_bug.cgi?id=671#c59
I don't feel like this logic can be moved to our needs, at least it'll need a
significant wording update.

https://bugs.libre-soc.org/show_bug.cgi?id=671#c64
I'm talking not only of can it be done or not, but also of the specs.
1. The specs wording is to be changed (e.g. for addg6s there should be no
mentioning of 16 bits, or double word); the whole wording should be
register-agnostic.
2. The pseudo-code should be updated respectively.

A short summary: if we intend to ever touch these, the current wording from the
spec does not leave us much room. These instructions _must_ be updated both in
specs and pseudo-code. You only consider the simplest one, addg6s, but even
that one needs changes. If we're OK with changing the specs and the original
semantics -- let's do it.

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