[Libre-soc-bugs] [Bug 731] potential design oversight in Partitioned SimdSignal Cat/Assign/etc lhs/rhs

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=731

--- Comment #18 from Jacob Lifshay <programmerjake at gmail.com> ---
Does it pass:

a = SimdSignal(...)
b = SimdSignal(...)
c = SimdSignal(...)
d = SimdSignal(...)

cat = Cat(a, b)

m.d.comb += cat.eq(c)
m.d.comb += d.eq(cat)

I expect not, since you fell into the trap that each PartitionedCat would only
ever be used on the lhs or the rhs, not both. SwizzledSimdValue correctly
handles this.

Also, does it handle:
a = SimdSignal(...)
b = SimdSignal(...)
c = SimdSignal(...)
d = SimdSignal(...)

cat = Cat(a, b)

m.d.comb += Cat(cat, c).eq(d) # two stages of Cat

I also expect not, SwizzledSimdValue also correctly handles this case, because
it is designed to handle assignments through any number of Cat and Slice calls.

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