[Libre-soc-bugs] [Bug 731] potential design oversight in Partitioned SimdSignal Cat/Assign/etc lhs/rhs

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=731

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
so, jacob, to recap there:

* 1 line of code: a hack backlink was made in the PCat function
  which allowed the signal containing the result to know the
  submodule that *produced* that result
* 4 lines of code: Partitioned Assign detected that hack and
  set a flag LHS/RHS
* 3 lines of code: ParttitionedCat based on that flag performs
  a LHS Cat instead of a RHS Cat.

eight - EIGHT - lines of code (not 400 replacing and regressing
existing classes and setting us back over a week)
excluding explanation, exploration, unit tests
and comments, all of which far exceed the additions themselves.

it doesn't have to be pretty, it doesn't need to fulfil future
needs, it has to do what is immediately needed in the shortest
timescale with the least fuss and in a way that at no time
destroys confidence in or undermines preexisting code.

turns out that PAssign does not need to worry about lengths,
i have no idea why but am not in the least bit going to
be concerned about it.  i suspect that on investigation
it will turn out that nmigen does deal with two assigns
somehow, by identifying the in/out direction.

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