[Libre-soc-bugs] [Bug 731] potential design oversight in Partitioned SimdSignal Cat/Assign/etc lhs/rhs

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=731

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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           See Also|                            |https://bugs.libre-soc.org/
                   |                            |show_bug.cgi?id=719

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
firstly, some unit tests need writing (in test_partsig.py),
it does not matter if they fail, that indicates a need to be
fixed.

examining PartitionedCat as an example, the flaw is anticipated
but not yet confirmed to be here:

 112                 with m.Case(pbit):
 113                     # direct access to the underlying Signal
 114                     comb += self.output.sig.eq(Cat(*output))

this is expected only to cope with RHS.  the option would therefore
be required for the following:

                      comb += Cat(*output).eq(self.input)


but, paradoxically, this results in exactly the same code because
output has to be followed up with an assignment to self.output.sig
anyway.

thus, we conclude that for "lhs" mode there must be a *list of outputs*
rather than as is the case currently only a list of *inputs*.

determining which mode to use, unfortunately, cannot be determined until
the actual Assignment takes place!

therefore, Assignment must actually perform an analysis of its lhs and
rhs arguments and set which mode (lhs or rhs) they are set to!

this is a rather large piece of work so should only be done if it
turns out to be entirely necessary, and, furthermore, evaluated against
whether the existing HDL can be adopted to avoid LHS AST assignments,
temporarily.  there are a number of known uses of Cat for example

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