[Libre-soc-bugs] [Bug 731] New: potential design oversight in Partitioned SimdSignal Cat/Assign/etc lhs/rhs

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=731

            Bug ID: 731
           Summary: potential design oversight in Partitioned SimdSignal
                    Cat/Assign/etc lhs/rhs
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

nmigen allows constructs such as:

     m.d.comb += Cat(a, b).eq(c)

which places the AST Construct on the left side not the right.
this is unlikely to have been forseen in the original Partitioned
submodule designs for PartitionedCat, PartitionedRepl, PartitionedAssign
etc. which may only cope at present with the AST Construct being on
the rhs:

     m.d.comb += c.eq(Cat(a, b))

this needs investigation and potentially correcting

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