[Libre-soc-bugs] [Bug 644] MP3: Basic SV impl
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Mon Jun 28 19:26:29 BST 2021
https://bugs.libre-soc.org/show_bug.cgi?id=644
--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
done
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=ea780569b30b81b07e20e4cba53673203df24af2
* pretend-predicate 0b01111 added
* loop count increased to 5
* MULH3 on icos36h works out to be exactly as
the hard-coded constants 16, 17, 9+4, 8-4 etc.
* hard-coded block now removed.
interestingly it wasn't as straightforward as i first imagined,
but retrospectively it's logical: s1 and s2 are initially created
from t1 and t0, the name-changes of the variables in the last
(now deleted) block confused me.
the predicate mask can be hard-coded to 0b01111 with an immediate,
which results in t1, s2 and t3 being set to zero on that last block.
i'll add some comments.
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