[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #94 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #91)
> the P&R completed for the whole chip, including the PowerISA core this time.
> it is 4x bigger @ 26,000 x 26,000 lambda
> 
> nohup.out is here: https://ftp.libre-soc.org/nohup.out.bz2
> 
> 3 horiz not routed, 2 vertical, but 7,000 unrouted segments.

  No no. 7 unrouted segments (4 Verticals, 3 Horizontals),
  7075 is the cumulated length of those segments, that is
  7075 lambdas.

> could the introduction of a clock tree (USE_CLOCKTREE=yes in Makefile)
> have an effect?

  Yes... The H-Tree consume more routing resources than a "default"
  routing. Nevertheless, it is not that much saturated as show the
  global routing which converge in 2 iterations only.
    That will be fixed after the HFNS, because the HFNS will also
  increase the problem.

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