[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #92 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #90)
> https://libre-soc.org/180nm_Oct2020/2020-09-30_19-13.png
> 
> hmmm, jean-paul: some of the pins are coming in from almost 100% the
> opposite side.  it seems that there is no... "weighted influence" on
> where the cells associated with the I/O should be placed.
> 
> could this be solved algorithmically (with a "this I/O pad pin please
> give it 5% weighting to put its cells closer to the pin" style algorithm)

  I just completed the whole chip P&R, I used the bba238c commit.
  Everything seems to have gone fine. I/O pads are more or less well
  placed (no more than the length of the side). It is already done,
  I/O pad should attract the cells they are connected to. But it is
  a weak influence compared to their connexion inside the chip.
  But I only get 35K gates for the core, is this normal ?

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