[Libre-soc-bugs] [Bug 508] decide package size and pin allocation for 180nm ASIC

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=508

--- Comment #7 from Staf Verhaegen <staf at fibraservi.eu> ---
> is it best to do an io ring that roughly matches that?
> 
> N: 38
> S: 38
> E: 26
> W: 26
> 
> or can we get away with 32-32-32-32?

The inner lead frame has 32 IO connections on each side so the latter.

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