[Libre-soc-bugs] [Bug 485] Create I-Cache from microwatt icache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=485

--- Comment #20 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #17)
> (In reply to Cole Poirier from comment #11)
> 
> > 1236                     for i in range(NUM_WAYS):
> > 1237                         with m.If(i == replace_way):
> > 1238                             comb += tagset.eq(cache_tags[r.store_index])
> > 1239                             comb += write_tag(i, tagset, r.store_tag)
> > 1240                             sync += cache_tags[r.store_index].eq(tagset)
> > ```
> > 
> > At first I only changed line 1238 to comb, but got a nmigen error about
> > trying to drive tagset from comb and sync domains, changing line 1239 to
> > comb as well fixed that error.
> 
> err... errr... yes!  exactly the same pattern as with cv, a few lines above.
> 
> copy into a temp var using comb.  modify.  store back.
> 
> btw the use of write_tag there will result in some awful code but we sort
> that later.

Tried to do that, is this correct:
```
1236 for i in range(NUM_WAYS):
1237     with m.If(i == replace_way):
1238         ts = Signal(INDEX_BITS)
1239         comb += ts.eq(cache_tags[r.store_index])
1240         comb += ts.bit_select(i, TAG_BITS).eq(
1241                  r.store_tag
1242                 )
1243         comb += tagset.eq(ts)
1244         sync += cache_tags[r.store_index].eq(tagset)
```

The code for write_tag for quick reference:
```
def write_tag(way, tagset, tag):
    return tagset[way * TAG_BITS:(way + 1) * TAG_BITS].eq(tag)
```

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