[Libre-soc-bugs] [Bug 475] cxxsim improvements

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Sep 27 17:40:06 BST 2020


--- Comment #14 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #13)
> it is quite normal to expect the remaining bits (MSBs) to be set to zero,
> and also for any bits that will not fit in the LHS to be thrown away.
> this for example is how all 1s are set: x.eq(~0) or x.eq(-1) where x is
> unsigned and way less than 64 bit.

Any non-zero update triggers the issue, provided that the signal being updated
has a width greater than 32 bits.

For instance, in my trials, alu_fsm.py and alu_hier.py were not affected. This
is because they instance 8-bit and 16-bit ALUs in their unit tests. I can
easily make them hang by instancing a 64-bit ALU instead.

On the other hand, compalu_multi hangs because the imm_data field in the
CompALUOpSubset Record is hardcoded to be 64 bits.

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