[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat Sep 26 00:52:06 BST 2020


--- Comment #76 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
jean-paul, staf may have been in touch with you already: i have the
IO connections done, now, with signals in the form:


which is the "standard" way of declaring IO connections where the
direction of the IOpad needs to be controlled by the ASIC.

i took a look at pxlib and these look like they match with piot_px.
but... there's nothing in ioring.py declaration about the direction,
despite e.g. the AM2901 example clearly having bi-directional pads.

how does that work?  i've located the AM2901 example which i can see
does have "inout" ports, however it's not obvious to me how the
"q3_from_pads" and "q3_to_pads" get turned into... you with me?


cumulus plugin IoPadConf.

entries in the chip dictionary, "pads.instances".

so anything in that entry will be explicitly declared (bi-directional)
and we can set the pin name ("GPIOA0") and set the in, out and oe.

however if we _don't_ set an entry in pads.instances, cumulus plugin
will "auto-detect" the pad type based on the name and so on.

Staf if you make something like pxlib, we can set the cell library
name using a config option in ioring.py

we have one example here - line 6 - where the pad cell library
is set to "pxlib":


but, Jean-Paul: Staf would like to be able to allow people to set the
drive strength.  this would be something that should go into additional
options in IoPadConf in the cumulus plugin.

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