[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #75 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #74)
> (In reply to Jean-Paul.Chaput from comment #73)
> >     As long as the routing complete, this kind of density is not
> >   a problem.
> 
> ahh ok.

  The idea is to achieve the highest density possible *without*
  overflowing. This is a tricky objective...

> well, we are still around 17 incomplete routes (out of 100,000+)
> err no i'm out by an order of magnitude on that

  To be accurate, it is not "routes" but "segments" :-)
  After I finish the buffering algorithm, I go back to analyse that.
  I mostly need to refine the computation of the provisional density
  of a GCell to correctly guide the global routing.
  I get confirmation that in recent design (28nm and below)
  you have between 50% and 80% of buffers!

>      - Track Segment Completion Ratio ........................ 100% [1020210+18]
>      - Wire Length Completion Ratio ....................... 100% [61786063+1360]
>      - Wire Length Expand Ratio ........................... 4.07% [min:59367975]
>      - Unrouted horizontals ........................................ 88.89% [16]
>      - Unrouted verticals ........................................... 11.11% [2]
>      - Done in ............................................... 7m 4.86s, 846.8Mb
> 
> one *million* tracks!

  Yes, that's starting to be a good test bench for the P&R !
  (remember, segments, not tracks ;-)

  If you want to have an hint about the inner working of the detailed
  router I can send you a chapter I did write for one of my students.

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