[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Sep 22 20:22:17 BST 2020


--- Comment #17 from Staf Verhaegen <staf at fibraservi.eu> ---
Would be strange if such a bug would be there as I successfully tested JTAG
interface with openocd on FPGA.
See for example this video:
I don't know though if this was still using the VHDL version of the JTAG
interface or the nmigen one.

Anyway won't have time in near future to look deeper into this.

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