[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
okaay, here we go.  "make lvx" in soclayout experiments12


1. Executing RTLIL frontend.
Input filename: memory.il

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \memory
ERROR: Module `\SPBlock_512W64B8W' referenced in module `\memory' in cell
`\U$$0' is not part of the design.
mk/synthesis-yosys.mk:50: recipe for target 'memory.blif' failed
make: *** [memory.blif] Error 1


this is what i was expecting: there is no Cell Library for yosys to
"understand" the block named SPBlock_512W6B48W.  how is that solved?


commit 4b443ec0a071074334b29f3a972949a889f61cd4
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Tue Dec 22 15:02:32 2020 +0000

    add SPBlock_512W64B8W to memory.py

https://git.libre-soc.org/?p=soclayout.git;a=commitdiff;h=4b443ec0a071074334b29f3a972949a889f61cd4

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