[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #11)
> Currently I SPBlock_512W64B8W as name of the 4K SRAM block.

ah! this was part of the missing information for the puzzle :)

> This should be
> the nmigen code to include it:
> 
>     a = Signal(9)
>     q = Signal(64)
>     d = Signal(64)
>     we = Signal(8)
>     sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d, i_we=we)
>     m.submodules += sram

ahh goood, perfect.  so this will not conflict with yosys detection of
Memory/arrays at all. excellent.

based on this, creating a tiny example for soclayout called experiments12
should be very easy.

> How to do the conversion to litex I don't know.

that's why i suggested doing an extremely simple example (not involving litex
at all).

i may have to create a special wishbone peripheral for this (mostly cut/paste
of the way that litex does SRAM) so as to keep it separate.

then, the standard litex "SocCore.add_sram()" litex function will create Memory
(which yosys turns to DFF), the special peripheral creates the 
SPBlock_512W64B8W instance.


> Using this should allow to generate Verilog netlist that instantiates the
> SRAM blocks.

fanntastic.

to complete a "make lvx", on the tiny example, will a special (new) Cell
Library be needed, one that contains one item: SPBlock_512W64B8W?

or, is there something else going on?

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