[Libre-soc-bugs] [Bug 458] PartitionedSignal needs nmigen constructs "m.If", Switch etc

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=458

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://github.com/nmigen/nmigen/blob/59ef6e6a1c4e389a41148554f2dd492328820ecd/nmigen/hdl/dsl.py#L447

ah ha!

this is the location where the code-fragments for m.If/Elif/Else are
generated, and it should be really pretty straightforward to drop the
appropriate replacement (parallel, SIMD) statements in at this location, with a
replacement (override) of Module._pop_ctrl

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