[libre-riscv-dev] [Bug 270] investigate nmigen clock gating

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sat Mar 28 16:20:53 GMT 2020


Staf Verhaegen <staf at fibraservi.eu> changed:

           What    |Removed                     |Added
                 CC|                            |staf at fibraservi.eu

--- Comment #2 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
> > The principle is that you save power by not clocking the parts of the circuit
> > that don't have to do any computing. I think this could be a more
> > general way to only enable the stages in your pipeline who actually 
> > are doing computation.
> ok so if i understand this correctly:
> * the clock still runs at 1600mhz
> * the clock runs a cyclic shift-register of length equal to the
>   number of stages, at 1600 mhz.
> * only every *alternate* one of those elements in the shift register
>   is enabled (or, if you want full speed, all of them). 
> * through EnableInserter each stage is clocked by a *different* bit
>   in the shifted-register

Correct, the clock is the pipeline clock. In theory other parts of the CPU
could for example run at half the clock frequency. This will then naturally
automatically only committing a new operation every other cycle at maximum.

I did not test it but EnableInserter should work in simulation and FPGA.
Depending on FPGA you likely won't see the full power improvements as I think
that the enabling is implemented as an enable input to each FF and not with
gating parts of the clock tree. It will still guarantee that the output of FFs
don't change.
As said implementing clock gating for ASICs will not be a simple task.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list