[libre-riscv-dev] [Bug 270] investigate nmigen clock gating

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=270

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
> The principle is that you save power by not clocking the parts of the circuit
> that don't have to do any computing. I think this could be a more
> general way to only enable the stages in your pipeline who actually 
> are doing computation.

ok so if i understand this correctly:

* the clock still runs at 1600mhz
* the clock runs a cyclic shift-register of length equal to the
  number of stages, at 1600 mhz.
* only every *alternate* one of those elements in the shift register
  is enabled (or, if you want full speed, all of them). 
* through EnableInserter each stage is clocked by a *different* bit
  in the shifted-register

> That said I think this feature does not fit in the MVP scope of the October
> prototype so that chip should IMO not use clock gating nor the pass-through
> register feature from the original discussion. 

no, i agree, and, more to the point, we don't need it for the 180nm ASIC
(except perhaps to test the concept).

one thing that we have is, the use of OO python has the entirety of the
stages themselves *completely* separated firmly behind a general-purpose
API, where the construction of pipelines, from those stages, using entirely
different pipeline techniques, is *literally* a one-line change.

so we could conceivably do the *entire* suite of pipelines - convert them
to use this clock gating technique - *literally* in well under a day,
after first experimenting with EnableInserter and a quick and simple unit
test.

re-running the IEEE754 FP unit tests on the other hand... *sigh* :)

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