[libre-riscv-dev] Clock Gating (was cache SRAM organisation)

[Luke Kenneth Casson Leighton]

On Sat, Mar 28, 2020 at 2:08 PM Staf Verhaegen <staf at fibraservi.eu> wrote:

> There is an (IMO better) alternative for what you are doing with your pass-through registers and that is clock gating (wikipedia, allaboutcircuits).

ok that's very valuable and appreciated.  will reply here
http://bugs.libre-riscv.org/show_bug.cgi?id=270