[libre-riscv-dev] Clock Gating (was cache SRAM organisation)

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Mar 28 14:26:09 GMT 2020

On Sat, Mar 28, 2020 at 2:08 PM Staf Verhaegen <staf at fibraservi.eu> wrote:

> There is an (IMO better) alternative for what you are doing with your pass-through registers and that is clock gating (wikipedia, allaboutcircuits).

ok that's very valuable and appreciated.  will reply here

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