[libre-riscv-dev] [Bug 269] New: auto-conversion / parser of POWER ISA Spec v3.0B

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=269

            Bug ID: 269
           Summary: auto-conversion / parser of POWER ISA Spec v3.0B
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

see
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-March/005470.html
and
http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/2020-March/000007.html

the idea is, rather than write the simulator (and hardware) by hand
(which will be tedious, slow, and full of mistakes), parse the pseudo-code
*in the spec*, and turn it into *actual code*.

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