[libre-riscv-dev] extremely busy crowdsupply update started
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri Mar 27 19:20:38 GMT 2020
On Fri, Mar 27, 2020 at 4:35 PM Tobias Platen
<libre-soc at platen-software.de> wrote:
> On Fri, 27 Mar 2020 15:49:45 +0000
> Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> I've cloned the repository and now I could write something to fill one or more TODOs in the file 023_2020mar26_decoder_emulator_started.mdwn probably either Coriolis2 experimentation started or POWER ISA decoder and Simulator.
sure - i've added you to the repo so you can git push to it.
> I think I'll work on the POWER ISA decoder and Simulator next.
i had an idea about that, based on this:
my feeling is, we're wasting our time trying to "manually" create both
a processor and also a simulator, from "scratch", when there are
perfectly good, machine-readable expressions (at least for the integer
instructions), like this:
34 RT RA D
0 6 11 16 31
if RA = 0 then b <= 0
else b <= (RA)
EA <= + EXTS(D)
RT <= 56^0 || MEM(EA, 1)
i'm advocating, therefore, that we *literally* parse the PDF spec,
create an "interpreter" for those fragments, then auto-generate code
and HDL from them.
mulhwu RT,RA,RB (Rc=0)
mulhwu. RT,RA,RB (Rc=1)
31 RT RA RB / 11 Rc
0 6 11 16 21 22 31
prod0:63 <- (RA)32:63 x (RB)32:63
RT32:63 <- prod0:31
RT0:31 <- undefined
those really don't look very hard, to turn into code, do they?
FP is a little more challenging because they use "words" to describe
most aspects of the hardware. oh wait! Appendix A p775 v3.0B
contains FP to rounding algorithms, and a few more besides.
i would not be at all surprised if, should we do document-parsing, we
had an entire simulator for the integer V3.0 system in a week, and the
hardware in around 2.
More information about the libre-riscv-dev