[libre-riscv-dev] cache SRAM organisation
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri Mar 27 10:59:30 GMT 2020
On Fri, Mar 27, 2020 at 10:36 AM Staf Verhaegen <staf at fibraservi.eu> wrote:
> Yes and no, it is the basic functionality of a pipeline :(
> You have the same latency but can have double the number of operations in flight.
yes. hence why it is so important to have, because double the number
of operations means that we need double the number of Function Units
in the Dependency Matrix in order to keep the entire out-of-order
also, double the number of operations in flight means that we need
double the number of Branch Prediction Units, and much more complex
BPUs at that, just to deal with the (now very likely) scenario of
having far more overlapping inner loops "in flight".
all this from just extending the pipeline length(s) from 5 to 10. so
it's not just a "nice-to-have" feature, it's actually really important
to keeping the overall size of the chip down.
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