[libre-riscv-dev] cache SRAM organisation

Staf Verhaegen staf at fibraservi.eu
Fri Mar 27 10:36:15 GMT 2020

Luke Kenneth Casson Leighton schreef op vr 27-03-2020 om 09:44 [+0000]:
> On Fri, Mar 27, 2020 at 9:25 AM Staf Verhaegen <staf at fibraservi.eu> wrote:
> > My point is that you will have the same performance for the fixed 5-stage pipeline running @ 800MHz
> no, it won't: it'll be half the clock speed.  it won't be double thenumber of computations: it'll be the exact same number ofcomputations.  therefore, half the speed means half the number ofcomputations because the *throughput* is the same
> when you use "cpufreq-set" to change the clock rate, if the clock rateis halved, the computer is twice as slow.

You are right.

> yes it's confusing :)

Yes and no, it is the basic functionality of a pipeline :(
You have the same latency but can have double the number of operations in flight.


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