[libre-riscv-dev] [Bug 267] New: The efficiency of adder/subtractor

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Thu Mar 26 22:05:29 GMT 2020


            Bug ID: 267
           Summary: The efficiency of adder/subtractor
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Windows
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: ALU (including IEEE754 16/32/64-bit FPU)
          Assignee: lkcl at lkcl.net
          Reporter: tanner.of.kha at gmail.com
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

>From the task http://bugs.libre-riscv.org/show_bug.cgi?id=217

(In reply to Luke Kenneth Casson Leighton from comment #42)
> (In reply to Jock Tanner from comment #41)
> > I think most ALUs
> > just negate and add instead of subtract. I think this would use a bit less
> > logic, and negation in itself is also a useful operation.
> yes. in the "real" alu we have... mmm... not sure, actually.  probably -
> do me a favour and raise a bugreport as a reminder to look up what
> rocketchip does?

Actually I was thinking about what Harris&Harris suggested in their famous
book. You just have to have an inverter on one operand input of an adder. The
two's complement of that operand can be achieved via the carry input.

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