[libre-riscv-dev] cache SRAM organisation

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Mar 26 21:28:32 GMT 2020

On Thu, Mar 26, 2020 at 8:08 PM Staf Verhaegen <staf at fibraservi.eu> wrote:

> Luke Kenneth Casson Leighton schreef op do 26-03-2020 om 15:15 [+0000]:
> > On Thursday, March 26, 2020, Staf Verhaegen <staf at fibraservi.eu> wrote:
> > > I can understand you do this to implement functional units withconfigurable pipeline length but I would strongly discourage to pipelineregister files after each other .
> >
> >
> > "pipeline register files after each other"? apologies i am not clear whatyou mean, here.  do you mean "don't do write-thru on the Regfile"?
> No I meant for example connecting the output of one port of an asynchronous RAM to for example the address input of another port of an asynchronous RAM.

ah right, no definitely not.  the connections are:

RegisterFile readport[0..R] ==> FunctionUnit[0..M] operand latches
                                            pipeline stage 0
                                            pipeline stage 1
                                            pipeline stage N
RegisterFile writeport[0..W] <== FunctionUnit[0..M] result latches

(and also: )
register file bypass forwardingbus <== FunctionUnit result latches
register file bypass forwardingbus ==> FunctionUnit operand latches

so the asynchronous SRAMs will definitely *only* be connected to SFF
latches.  *not* to other asynchronous SRAMs.

appreciated the clarification.


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