[libre-riscv-dev] cache SRAM organisation

Staf Verhaegen staf at fibraservi.eu
Thu Mar 26 20:08:04 GMT 2020

Luke Kenneth Casson Leighton schreef op do 26-03-2020 om 15:15 [+0000]:
> On Thursday, March 26, 2020, Staf Verhaegen <staf at fibraservi.eu> wrote:
> > I can understand you do this to implement functional units withconfigurable pipeline length but I would strongly discourage to pipelineregister files after each other .
> "pipeline register files after each other"? apologies i am not clear whatyou mean, here.  do you mean "don't do write-thru on the Regfile"?

No I meant for example connecting the output of one port of an asynchronous RAM to for example the address input of another port of an asynchronous RAM.


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