[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #130 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://github.com/antonblanchard/microwatt/blob/master/ppc_fx_insns.vhdl#L110
ppc_adde():
return 65-bit RA + 65-bit RB + carry

https://github.com/antonblanchard/microwatt/blob/master/ppc_fx_insns.vhdl#L140
ppc_add():
return 64-bit RA + 64-bit RB

hmm ppc_add() doesn't appear to be used (at all) in execute1.vhdl

decode_input_carry(ic, XERC) is:
if ic=ZERO return 0
if ic=ONE return 1
if ic=CA return XERC.ca

returning XERC.ca might be a significant difference, there... ah!  yes,
if you look in the "cry_in" column, adde and addeo are supposed to take
cry_in=CA *not* cry_in=ZERO.

that's likely to be it.

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